Anindya Sundar Dhar: шукати на сайті Z-Library

Ghosh, Kausik, Dhar, Anindya Sundar

Рік:

2018

Мова:

english

Файл:

PDF, 4.23 MB

english, 2018

A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation

Журнал:

Journal of Real-Time Image Processing

Рік:

2016

Мова:

english

Файл:

PDF, 541 KB

english, 2016

CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis

Kailash Chandra Ray, Anindya Sundar Dhar

Журнал:

Ayan Banerjee, Anindya Sundar Dhar

Рік:

2014

Мова:

english

Файл:

PDF, 525 KB

english, 2014

Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer

Журнал:

Ghosh, Kausik, Dhar, Anindya Sundar

Рік:

2013

Мова:

english

Файл:

PDF, 1.00 MB

english, 2013

Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation

Журнал:

Journal of Real-Time Image Processing

Рік:

2016

Файл:

PDF, 112 KB

2016

[IEEE 2014 IEEE Students' Technology Symposium (TechSym) - Kharagpur (2014.2.28-2014.3.2)] Proceedings of the 2014 IEEE Students' Technology Symposium - Double-fault tolerant architecture design for digital adder

Рік:

2014

Мова:

english

Файл:

PDF, 364 KB

english, 2014

Real-time fault-tolerance with hot-standby topology for conditional sum adder

Microelectronics Reliability

Журнал:

Рік:

2015

Мова:

english

Файл:

PDF, 896 KB

english, 2015

Fault tolerant architecture design using quad-gate-transistor redundancy

IET Circuits Devices & Systems

Журнал:

Рік:

2015

Мова:

english

Файл:

PDF, 489 KB

english, 2015

High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation

Mukherjee, Rohan, Mahajan, Vikrant, Dhar, Anindya Sundar, Chakrabarti, Indrajit

Журнал:

Journal of Circuits System and Computers

Рік:

2016

Мова:

english

Файл:

PDF, 257 KB

english, 2016

High-performance VLSI architectures for M-PSK modems

Mamidala, Chandrakanth, Dhar, Anindya Sundar

Журнал:

IET Circuits Devices & Systems

Рік:

2017

Мова:

english

Файл:

PDF, 578 KB

english, 2017

CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism

Ray, Kailash Chandra, Dhar, Anindya Sundar

Журнал:

Roy, Avishek Sinha, Dhar, Anindya Sundar

Рік:

2018

Мова:

english

Файл:

PDF, 1.47 MB

english, 2018

[IEEE 2018 IEEE International Symposium on Circuits and Systems (ISCAS) - Florence, Italy (2018.5.27-2018.5.30)] 2018 IEEE International Symposium on Circuits and Systems (ISCAS) - A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders

Рік:

2018

Мова:

english

Файл:

PDF, 595 KB

english, 2018

SIBAM-SIgn Inclusive Broken Array Multiplier Design for Error Tolerant Applications

Roy, Avishek Sinha, Dhar, Anindya Sundar

Журнал:

IEEE Transactions on Circuits and Systems II: Express Briefs

Рік:

2020

Файл:

PDF, 576 KB

2020

A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation

Banerjee, Ayan, Dhar, Anindya Sundar

Журнал:

Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee

Рік:

2020

Файл:

PDF, 2.10 MB

2020

Architectural design and FPGA implementation of radix-4 CORDIC processor

Журнал:

Microprocessors and Microsystems

Рік:

2010

Мова:

english

Файл:

PDF, 704 KB

english, 2010

Adaptive digital phase modulation schemes using transition-initiated phase acceleration

Rajarshi Mahapatra, Anindya Sundar Dhar, Debasish Datta

Журнал:

AEU - International Journal of Electronics and Communications

Рік:

2008

Мова:

english

Файл:

PDF, 379 KB

english, 2008

Integrated voice and data transmission employing adaptive modulation in wireless networks

Rajarshi Mahapatra, Anindya Sundar Dhar, Debasish Datta

Журнал:

AEU - International Journal of Electronics and Communications

Рік:

2009

Мова:

english

Файл:

PDF, 504 KB

english, 2009

An array architecture for computing two-dimensional discrete Hartley transforms

Anindya Sundar Dhar, Swapna Banerjee

Журнал:

Computers & Electrical Engineering

Рік:

1991

Мова:

english

Файл:

PDF, 398 KB

english, 1991

Multiplierless array architecture for computing Discrete Cosine Transform

Manik Chandra Mandal, Anindya Sundar Dhar, Swapna Banerjee

Журнал:

Computers & Electrical Engineering

Рік:

1995

Мова:

english

Файл:

PDF, 432 KB

english, 1995

[IEEE 2012 Annual IEEE India Conference (INDICON) - Kochi, India (2012.12.7-2012.12.9)] 2012 Annual IEEE India Conference (INDICON) - VLSI architectural design of zoomable real time spectrum analyzer

Sarkar, Sumantra, Dhar, Anindya Sundar

Рік:

2012

Мова:

english

Файл:

PDF, 1.12 MB

english, 2012

[IEEE 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) - Seattle, WA, USA (2010.08.1-2010.08.4)] 2010 53rd IEEE International Midwest Symposium on Circuits and Systems - Modified Elmore delay model for VLSI interconnect

Mal, Ashis Kumar, Dhar, Anindya Sundar

Рік:

2010

Мова:

english

Файл:

PDF, 422 KB

english, 2010

[IEEE 2014 18th International Symposium on VLSI Design and Test (VDAT) - Coimbatore, India (2014.7.16-2014.7.18)] 18th International Symposium on VLSI Design and Test - VLSI design of fast fractal image encoder

Panigrahy, Mamata, Chakrabarti, Indrajit, Dhar, Anindya Sundar

Рік:

2014

Мова:

english

Файл:

PDF, 1.39 MB

english, 2014

[IEEE APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems - Kuala Lumpur, Malaysia (2010.12.6-2010.12.9)] 2010 IEEE Asia Pacific Conference on Circuits and Systems - Design of DXT architecture using current switched integrator

Mal, Ashis Kumar, Hari, Om Prakash, Todani, Rishi, Dhar, Anindya Sundar

Рік:

2010

Мова:

english

Файл:

PDF, 354 KB

english, 2010

[IEEE 2012 25th International Conference on VLSI Design - Hyderabad, India (2012.01.7-2012.01.11)] 2012 25th International Conference on VLSI Design - Random Access Analog Memory (RA2M) for Video Signal Application

Chattaraj, Nilanjan, Dhar, Anindya Sundar

Рік:

2012

Мова:

english

Файл:

PDF, 412 KB

english, 2012

[IEEE 2012 International Symposium on Electronic System Design (ISED) - Kolkata, India (2012.12.19-2012.12.22)] 2012 International Symposium on Electronic System Design (ISED) - Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture

Nandi, Prajit, Sahu, Debashis, Dhar, Anindya Sundar, Das, Soumen

Рік:

2012

Мова:

english

Файл:

PDF, 367 KB

english, 2012

SPICE compatible behavioural modelling of resistive sensors

Журнал:

Measurement Science and Technology

Рік:

2014

Мова:

english

Файл:

PDF, 1.64 MB

english, 2014

High Performance VLSI Architecture for Three-Step Search Algorithm

Mukherjee, Rohan, Sheth, Keyur, Dhar, Anindya Sundar, Chakrabarti, Indrajit, Sengupta, Somnath

Журнал:

Ray, Kailash Chandra, Dhar, Anindya Sundar

Рік:

2015

Мова:

english

Файл:

PDF, 1.19 MB

english, 2015

[IEEE 2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN) - Surat, India (2014.12.26-2014.12.27)] 2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking - Parallel architecture for real time computation of discrete Mellin transform

Рік:

2014

Мова:

english

Файл:

PDF, 125 KB

english, 2014

[IEEE 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Kolkata, India (2016.1.4-2016.1.8)] 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs

Рік:

2016

Мова:

english

Файл:

PDF, 803 KB

english, 2016

Choice of granularity for reliable circuit design using dynamic reconfiguration

Microelectronics Reliability

Журнал:

Рік:

2016

Мова:

english

Файл:

PDF, 2.73 MB

english, 2016

Effect of single-dose carbapenem exposure on transcriptional expression of blaNDM-1 and mexA in Pseudomonas aeruginosa

Choudhury, Debarati, Paul, Deepjyoti, Ghosh, Anindya Sundar, Das Talukdar, Anupam, Dutta Choudhury, Manabendra, Maurya, Anand Prakash, Dhar (Chanda), Debadatta, Chakravarty, Atanu, Bhattacharjee, Amit

Журнал:

Journal of Global Antimicrobial Resistance

Рік:

2016

Мова:

english

Файл:

PDF, 346 KB

english, 2016

[IEEE 2016 Twenty Second National Conference on Communication (NCC) - Guwahati, India (2016.3.4-2016.3.6)] 2016 Twenty Second National Conference on Communication (NCC) - Hardware implementation of quadtree based fractal image decoder

Panigrahy, Mamata, Chakrabarti, Indrajit, Dhar, Anindya Sundar

Рік:

2016

Мова:

english

Файл:

PDF, 439 KB

english, 2016

[IEEE TENCON 2016 - 2016 IEEE Region 10 Conference - Singapore (2016.11.22-2016.11.25)] 2016 IEEE Region 10 Conference (TENCON) - CORDIC-based parallel architecture for one dimensional discrete Mellin transform

Ray, Kailash Chandra, Dhar, Anindya Sundar

Рік:

2016

Мова:

english

Файл:

PDF, 10.21 MB

english, 2016

Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities

Mula, Subrahmanyam, Gogineni, Vinay Chakravarthi, Dhar, Anindya Sundar

Журнал:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Рік:

2017

Мова:

english

Файл:

PDF, 3.79 MB

english, 2017

Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations

Journal of Electronic Testing

Журнал:

Рік:

2017

Мова:

english

Файл:

PDF, 2.39 MB

english, 2017

Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics

Sarkar, Sumantra, Biswas, Ayan, Dhar, Anindya Sundar, Rao, Rahul M.

Журнал:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Рік:

2017

Мова:

english

Файл:

PDF, 5.00 MB

english, 2017

Triple transistor based fault tolerance for resource constrained applications

Ray, Kailash Chandra, Prasad, M. V. N. V., Dhar, Anindya Sundar

Журнал:

Microelectronics Journal

Рік:

2017

Мова:

english

Файл:

PDF, 825 KB

english, 2017

An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform

Журнал:

Roy, Avishek Sinha, Prasad, N, Dhar, Anindya Sundar

Рік:

2017

Мова:

english

Файл:

PDF, 2.51 MB

english, 2017

[IEEE 2016 20th International Symposium on VLSI Design and Test (VDAT) - Guwahati, India (2016.5.24-2016.5.27)] 2016 20th International Symposium on VLSI Design and Test (VDAT) - Approximate conditional carry adder for error tolerant applications

Рік:

2016

Мова:

english

Файл:

PDF, 757 KB

english, 2016

[IEEE 2016 20th International Symposium on VLSI Design and Test (VDAT) - Guwahati, India (2016.5.24-2016.5.27)] 2016 20th International Symposium on VLSI Design and Test (VDAT) - High performance bit-sliced pipelined comparator tree for FPGAs

Рік:

2016

Мова:

english

Файл:

PDF, 1.27 MB

english, 2016

[IEEE 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Pune, India (2018.1.6-2018.1.10)] 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization

Рік:

2018

Мова:

english

Файл:

PDF, 1.89 MB

english, 2018

[IEEE 2017 IEEE 24th International Conference on High Performance Computing (HiPC) - Jaipur (2017.12.18-2017.12.21)] 2017 IEEE 24th International Conference on High Performance Computing (HiPC) - Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs

Mula, Subrahmanyam, Gogineni, Vinay Chakravarthi, Dhar, Anindya Sundar

Рік:

2017

Мова:

english

Файл:

PDF, 1.56 MB

english, 2017

Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification

Журнал:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Рік:

2018

Мова:

english

Файл:

PDF, 3.10 MB

english, 2018

Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method

Журнал:

Рік:

2018

Мова:

english

Файл:

PDF, 1.27 MB

english, 2018

[IEEE 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) - Vancouver, BC, Canada (2018.5.21-2018.5.25)] 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) - Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support

Рік:

2018

Файл:

PDF, 824 KB

2018

[IEEE 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) - Vancouver, BC, Canada (2018.5.21-2018.5.25)] 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) - Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support

Mula, Subrahmanyam, Gogineni, Vinay Chakravarthi, Dhar, Anindya Sundar

Рік:

2018

Мова:

english

Файл:

PDF, 824 KB

english, 2018

Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise

Журнал:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Рік:

2019

Файл:

PDF, 8 KB

2019

[IEEE 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Delhi, NCR, India (2019.1.5-2019.1.9)] 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - VLSI Architectures for Jacobi Symbol Computation

Рік:

2019

Мова:

english

Файл:

PDF, 748 KB

english, 2019

Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations